1. Field of the Invention
The present invention is generally in the field of semiconductor chip packaging. More specifically, the present invention is in the field of leadless chip carrier design and structure.
2. Background Art
The semiconductor fabrication industry is continually faced with a demand for smaller and more complex dies. These smaller and more complex dies must also run at higher frequencies. The requirement of smaller, more complex, and faster devices has resulted in new challenges not only in the fabrication of the die itself, but also in the manufacturing of various packages, structures, or carriers that are used to house the die and provide electrical connection to xe2x80x9coff-chipxe2x80x9d devices.
As an example, the demand for higher frequencies means, among other things, that xe2x80x9con-chipxe2x80x9d and xe2x80x9coff-chipxe2x80x9d parasitics must be minimized. For example, parasitic inductance, capacitance, and resistance, which all adversely affect electrical performance of the die and its associated off-chip components must be minimized. Since RF (xe2x80x9cRadio Frequencyxe2x80x9d) semiconductor devices run at high frequencies, those devices (i.e. RF devices) constitute a significant category of devices that specially require very low parasitics.
Recently, surface mount chips and chip carriers have gained popularity relative to discrete semiconductor packages. A discrete semiconductor package typically has a large number of xe2x80x9cpinsxe2x80x9d which may require a relatively large space, also referred to as the xe2x80x9cfootprint,xe2x80x9d to mount and electrically connect the discrete semiconductor package to a printed circuit board. Moreover, the cost and time associated with the manufacturing of the discrete semiconductor package and the cost and time associated with drilling a large number of holes in the printed circuit board are among additional reasons why alternatives such as surface mount devices and chip carriers have gained popularity.
There have been various attempts in the art to arrive at different chip carrier designs. Japanese Publication Number 10313071, published Nov. 24, 1998, titled xe2x80x9cElectronic Part and Wiring Board Device,xe2x80x9d on which Minami Masumi is named an inventor, discloses a structure in which to dissipate heat emitted by a semiconductor device. The structure provides metallic packed through-holes formed in a wiring board that transmit heat emitted from a bare chip through a heat dissipation pattern on the bottom of the wiring board, and then to a heat dissipation plate.
Japanese Publication Number 02058358, published Feb. 27, 1990, titled xe2x80x9cSubstrate for Mounting Electronic Component,xe2x80x9d on which Fujikawa Osamu is named an inventor, discloses a substrate with a center area comprising eight thermally conductive resin-filled holes sandwiched between metal-plated top and bottom surfaces. An electronic component is then attached to the center area of the top metal-plated surface of the substrate with silver paste adhesive to improve heat dissipation and moisture resistance.
Japanese Publication Number 09153679, published Jun. 10, 1997, titled xe2x80x9cStacked Glass Ceramic Circuit Board,xe2x80x9d on which Miyanishi Kenji is named an inventor, discloses a stacked glass ceramic circuit board comprising seven stacked glass ceramic layers. The multi-layer stacked glass ceramic circuit board further comprises a number of via holes comprising gold or copper with surface conductors on the top and bottom surfaces covering the via holes. The top conductor functions as a heat sink for an IC chip.
Japanese Publication Number 10335521, published Dec. 18, 1998, titled xe2x80x9cSemiconductor Device,xe2x80x9d on which Yoshida Kazuo is named an inventor, discloses a thermal via formed in a ceramic substrate, with a semiconductor chip mounted above the thermal via. The upper part of the hole of the thermal via is formed in a ceramic substrate in such a manner that it becomes shallower as it goes outward in a radial direction.
A conventional chip carrier structure for mounting a chip on a printed circuit board has a number of shortcomings. For example, conventional chip carriers still introduce too much parasitics and still do not provide a low inductance and resistance ground connection to the die. Conventional chip carriers also have a very limited heat dissipation capability and suffer from the concomitant reliability problems resulting from poor heat dissipation. As an example, in high frequency applications, such as in RF applications, several watts of power are generated by a single die. Since the semiconductor die and the chip carrier are made from different materials, each having a different coefficient of thermal expansion, they will react differently to the heat generated by the die. The resulting thermal stresses can cause cracking or a separation of the die from the chip carrier and, as such, can result in electrical and mechanical failures. Successful dissipation of heat is thus important and requires a novel structure and method.
The requirement of smaller, more complex, and faster devices operating at high frequencies, such as wireless communications devices and Bluetooth RF transceivers, has also resulted in an increased demand for small size, high quality factor (xe2x80x9chigh-Qxe2x80x9d) inductors. One attempt to satisfy the demand for small, high-Q inductors has been to fabricate on-chip inductors. However, size and line thickness limitations directly impact the quality factor obtainable in on-chip inductors. Discrete, xe2x80x9coff-chipxe2x80x9d inductors represent another attempt to satisfy the demand for small, high-Q inductors. However, discrete, xe2x80x9coff-chipxe2x80x9d inductors suffer from various disadvantages not shared by on-chip inductors. For example, the discrete, xe2x80x9coff-chipxe2x80x9d inductor requires the assembly of at least two components, i.e. the chip itself and the off-chip inductor. The required assembly of two or more components introduces corresponding reliability issues and also results in a greater manufacturing cost.
Additionally, off-chip inductors require relatively long off-chip wires and interconnect lines to provide electrical connection to the chip and to xe2x80x9coff-chipxe2x80x9d devices. The relatively long off-chip wires and interconnect lines result in added and unwanted parasitics. Further, the interconnects for off-chip inductors are subject to long-term damage from vibration, corrosion, chemical contamination, oxidation, and other chemical and physical forces. Exposure to vibration, corrosion, chemical contamination, oxidation, and other chemical and physical forces results in lower long-term reliability for off-chip inductors.
Thus, there is a need for a small, high-Q inductor that is embedded in the structure that houses and supports the semiconductor die. Additionally, the structure in which the high-Q inductor is embedded needs to provide low parasitics, efficient heat dissipation and a low inductance and resistance ground connection.
Moreover, there exists a need for a novel and reliable structure and method that houses, supports, and electrically connects a semiconductor die to an inductor embedded in the structure and which overcomes the problems faced by discrete inductors, discrete semiconductor packages, and conventional chip carriers. More specifically, there exists a need for a novel and reliable structure and method to embed an inductor in a structure that houses, supports and is electrically connected to a semiconductor die, while providing low parasitics, efficient heat dissipation and a low inductance and resistance ground.
The present invention is directed to structure and method for fabrication of a leadless chip carrier with embedded inductor. The present invention discloses a structure that provides efficient dissipation of heat generated by a semiconductor die. The present invention further discloses a structure that includes an embedded inductor and also provides low parasitics, and a low inductance and resistance ground connection to the semiconductor die.
In one embodiment, the present invention comprises a substrate having a top surface for receiving a semiconductor die. For example, the substrate can comprise an organic material such as polytetrafluoroethylene material or an FR4 based laminate material. By way of further example, the substrate can comprise a ceramic material. According to one aspect of the present invention, an inductor is patterned on the top surface of the substrate. The inductor is easily accessible by connecting its first and second terminals to, respectively, a substrate signal bond pad and a semiconductor die signal bond pad. In another aspect of the present invention, an inductor is fabricated within the substrate. The inductor comprises via metal segments connecting interconnect metal segments on the top and bottom surfaces of the substrate. The first and second terminals of the inductor are easily accessible through first and second substrate signal bond pads. The present invention may further comprise a printed circuit board attached to the bottom surface of the substrate.
In one embodiment, the invention comprises at least one via in the substrate. The invention""s at least one via provides an electrical connection between a signal bond pad of the semiconductor die and the printed circuit board. The at least one via can comprise an electrically and thermally conductive material such as copper. The at least one via provides an electrical connection between a substrate bond pad and the printed circuit board. The substrate bond pad is connected to the signal bond pad of the semiconductor die by a signal bonding wire. The at least one via also provides an electrical connection between the signal bond pad of the semiconductor die and a land that is electrically connected to the printed circuit board.